Cadence Backs User Demand for Accelerating IEEE P1647 e Standardization; Working Group Completes Technical Portion of LRM Ahead of Schedule; Standardization Vote Expected in Fourth Quarter of 2005
SAN JOSE, Calif.—(BUSINESS WIRE)—Oct. 17, 2005—
Responding to user demand for a proven standard
verification language, Cadence Design Systems, Inc. (NYSE:CDN)
(Nasdaq:CDN) today announced that it has stepped up its support for
the IEEE P1647 e standardization effort. Cadence has contributed
resources for technical editing and program management to ensure the
standard is of the highest quality and completed on time. The Cadence
contribution comes as increased participation and interest in the IEEE
working group has enabled a dramatic compression in the schedule for
completion. Technical content of the standard was completed June 6,
2005 four months ahead of schedule.
The e language is an extremely powerful and mature system-level
verification language that is in use today by an overwhelming majority
of industry leaders in consumer electronics, telecommunications,
semiconductors and IP. By standardizing the language within IEEE and
opening it up to development, customers will benefit as market-leading
products such as Specman Elite(R), which has been used to verify
thousands of designs, are joined by a burgeoning marketplace of
e-based tools. These complementary technologies will also be
accelerated to market by the openness and stability provided by an
IEEE-backed standard.
"LSI Logic has proven expertise in e and advanced verification
methodologies on complex IP blocks and entire systems. We have a
significant interest in the standardization of e and participated in
the drive toward e standardization by joining the LicenseE program in
2002," said Jeff Vanderlip, director of ASIC Marketing at LSI Logic.
"LSI Logic applauds Cadence's increased support for the IEEE P1647 e
standardization effort, and would like to see standardization of the e
language so that it is open and available to everyone."
"ARM(R) is fully supportive of the IEEE P1647 e standardization
effort and standards in general," said John Goodenough, director,
Design Technology, ARM. "e has been an integral part of our
verification methodology, and it is good to see it move closer to
standardization. We expect that this process will encourage the
proliferation of competitive tools based on the e language and will be
extremely positive for our partners since it ensures the stability of
e and provides them with a choice of tools."
Because of the complexities of today's designs, specialization of
engineering functions is becoming the rule rather than the exception.
This move to specialization emphasizes the fact that no single
language addresses everyone's needs in the verification cycle. For
example e has become the language of choice for verification
specialists, SystemVerilog serves design teams who need incremental
verification power and SystemC has become the language of choice for
system architects.
"Silicon Image's leadership in high-speed serial communications
cores depends on our IP working smoothly in our customers'
mixed-language design and verification flow, and we see e playing a
very important role," said Eric Almgren, vice president of business
development and IP licensing of Silicon Image, Inc. "From the
verification of our cores and delivery of verification IP in e to the
incredibly complex systems our customers develop, there is no way
you'll get your design out the door on schedule without supporting the
preferred language each specialist requires in the design chain."
With its Incisive(R) verification platform, Cadence offers the
only multi-language verification technology. The company's
all-inclusive position on verification languages benefits customers by
allowing each specialist an optimal blend of e, SystemC and
SystemVerilog languages. As the industry continues to drive standards,
each language will emerge and find its optimal place in the
verification landscape based on its strengths -- similar to incumbent
HDLs like Verilog(R) and VHDL.
"Novas' market-leading debug systems offer multi-language support
to align with the needs of the full range of specialists in the design
and verification flow. We have supported the e verification language
for several years to serve the needs of our customers using advanced
verification process automation," said Scott Sandler, CEO, of Novas.
"We fully support open standards; faster standardization of e will
benefit our customers and the language itself."
"With project and process level automation becoming more and more
critical, Cadence has come to the realization that the best way to
support customers is to offer support for standards that address the
needs of each specialist in the verification process," said Victor
Berman, director of Language Standards at Cadence. "We don't subscribe
to the approach that dictates to users the language they must use for
a given task. The bottom line is we support choice."
The IEEE initiated a ballot on the e LRM on Sept. 27, 2005. If the
ballot passes, the e functional verification language is expected to
be standardized by the IEEE by March 2006. For more information visit
www.ieee1647.org.
About Cadence
Cadence enables global electronic-design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence software and hardware,
methodologies, and services to design and verify advanced
semiconductors, printed circuit boards and systems used in consumer
electronics, networking and telecommunications equipment, and computer
systems. Cadence reported 2004 revenues of approximately $1.2 billion,
and has approximately 5,000 employees. The company is headquartered in
San Jose, Calif., with sales offices, design centers, and research
facilities around the world to serve the global electronics industry.
More information about the company, its products, and services is
available at www.cadence.com.
Cadence, the Cadence logo, Verilog, Incisive and Specman Elite are
registered trademarks of Cadence Design Systems in the United States
and other countries. Incisive is a trademark of Cadence Design
Systems.
ARM is a registered trademark of ARM Limited. "ARM" is used to
represent ARM Holdings plc; its operating company ARM Limited; and the
regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan;
ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium N.V.;
AXYS Design Automation Inc.; AXYS GmbH; ARM Embedded Technologies Pvt.
Ltd.; and ARM Physical IP, Inc.
All other trademarks are the property of their respective owners.
Contact:
Cadence Design Systems, Inc.
Ric Chope, 650-934-6820
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